-- LSI Design Contest in Okinawa 2010 -- decoder.vhd -- 2009/October/11th -- TASK: BCH(15,7) -- Copyright by Tom Wada@Univ. of the Ryukyus library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; entity DECODER is port (START : in std_logic; RBWE : in std_logic; START2 : out std_logic; RBEC : out std_logic; RESET : in std_logic; CLK : in std_logic ); end entity DECODER; architecture RTL of RECEIVER is -- HERE, WRITE YOUR ORIGINAL HDL CODE! -- GOOD LUCK! end architecture RTL;