1. Purpose

The contest this year are aiming for hardware design of the operation unit as a theme of "Deep Learning (Backpropagation)", conscious operations and cost calculation algorithm.

2．Design enviroment

MATLAB, Synopsys Synphony

Synopsys® Synphony Model™ Compiler

Synopsys® Synplify Pro® /Premier

Synopsys® Design Compiler®

Mathworks® MATLAB® /Simulink®

These environments will be listed in our response to the design environment.

Other logic synthesis tool

RTL handcoding( VHDL or Verilog-HDL)