Design Specification
1.Small RISC Processor
(SRP) architecture
5.Instruction ROM and
Data Memory
BASIC
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12th LSI Design ContestsEin Okinawa Design Specification - 7
8DData RAM operation
For Read operation, one of 32 words is selected by 6 bit address inputs. This read operation is completely combinational.
For Write operation, at Clock rising edge, if WE signal is asserted (=f1f), the input data Din is stored in the data memory.
Operational waveform is shown in
Figure 6: Data RAM operational waveform
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