16th LSI Design ContestsEin Okinawa  Design Specification - 3-1

3-1. Hardware Design Process

In this section, we describe about process of development. However, this process is a one of example. There are many methods to design hardware circuit, so please research other method, if you donft use this method.

3-1-1. Design Hardware Logic

In this part, we describe about model-base RTL design using Simulink, and we describe how to lap file into edf file.

Figure 21e

Figure 21

  • Model-base RTL design using Simulink

    • 1. We first start MATLAB software, next start Simulink tool on MATLAB. On top menu, we open design
          screen to select gFileh -> gnew fileh, after done it, Simulink library browser is started.

    Figure 22e

    Figure 22

    2. We can design HW circuit to select block which you want to use in library, and drag-and-drop that block
          into design screen. In this time, we plan to synthesize circuit by using Synplify, therefore we select
          Synphony HLS Blockset to design circuit.

    Figure 23e

    Figure 23

    3. After we designed a circuit, we use SHLSTool block of HLS Blockset to create HDL file (.v or .vhd).
          Please do following process to create HDL file. Double-click SHLSTool, open the implementation screen,
          and we decide implementation target device es information in this screen.

    Text 1
    Figure 24e

    Figure 24

    4. Disable Generate gClock-Reset Circuith of Clock Reset Options tab..

    Figure 25e

    Figure 25

    5. Please select the gAsynchronoush in Flip Flop Reset Sensitivity of Design Option tab.

    Figure 26e

    Figure 26

    6. We save setting parameter, and after that, we run that file. Then the Folder which include implemented
          file is created on MATLAB current folder.

          –It is possible to download the created Model file (here) from this folder.


  • Create a edf file via Synplify

    • 1. Wake the Synplify Preminer. Select gFileh ¨ gOpenh in top menu. Open the project file (fpga_hw_impl_1
          \verilog\fpga_hw.prj) created by SHLSTool, in the folder of Verilog. Click gImplementation Optionshon the
          left side of screen.

    2. Crick the gImplementation Optionsh in left menu.

    3. Check the gDisable I/O Insertionh ¨@Check the gOKh.

    Figure 27e

    Figure 27

    4. Execute (select the gRunh). The file, grev_1h, is created in g.fpga_hw_impl_1\verilogh. The .edf file is
          created in the file, grev_1h.

    5. Crick the gHDL-Analysth ¨ gRTLh ¨ gHierarchical Viewh in top menu.

    Figure 28e

    Figure 28

    6. We can show the created circuit structure of the .edf file.

    Figure 29e

    Figure 29

    –We can download the created .edf file (here) from this folder.

    Please contact me from here if you want the RTL source.

    3-1-2. Manual of Xilinx ISE and EDK

  • Running of gAC97h demo program

    • AC97 is attached to ATLYS board. To use gAC97 AUDIO CODECh, the development is used gAtlys_AC97_EDK_demoh which is demo project to control AC97 by MicroBlaze. This demo can be downloaded from ATLYSfs HP. In order to run this demo, EDK later

    versions of ISE13.2 is required. The following shows the execution procedure.


    1. Unzip the Atlys_AC97_EDK_demo.zip.

    2. Start the xps (Xilinx Platform Studio) that is a tool of EDK.

    3. Select gFileh?hOpen projecth from the menu at the top of the screen. Next Select gsystem.xmph in the
          project folder under the gAtlys_AC97_EDK_demo folderh.

    4. Click gHardwareh?hGenerate Netlisth from the menu at the top of the screen.

    Figure 30e

    Figure 30

    5. After completing implementation, select gProjecth?hExport Hardware Design to SDKh from the menu at
          the top of the screen.

    Figure 31e

    Figure 31

    6. Select the gExport & Launch SDKh.

    Figure 32e

    Figure 32

    7. Create a folder gSDK_Workh under the folder gSDK_Work Atlys_AC97_EDK_demo\projects \SDKh, and set
          it as workspace. Next click gOKh.

    Figure 33e

    Figure 33

    8. SDK is launched. Select gFileh?hNewh?gXilinx C Projecth from the menu at the top of the screen.

    Figure 34e

    Figure 34

    9. New Project is opened. Select the gEmpty Applicationh from the field gSelect Project Templateh. Next
          select hNexth.

    Figure 35e

    Figure 35

    10. Look see that the gCreate a new Board Support Package projecth has been selected, and click gFinishh.

    Figure 36e

    Figure 36

    11. Folder gBSP projecth and gproject Ch is added to the "Project Explorer".

    Figure 37e

    Figure 37

    12. Copy all files in gAtlys_AC97_EDK_demo\source\h to g
          Atlys_AC97_EDK_demo\project\SDK\SDK_Work\empty_application_0\srch. After that, right click in
          gProject Explorerh, and select hRefreshh. Then the Project is updated ,and source is added in the
          gProject Explorerh.

    Figure 38e

    Figure 38

    13. Select gBuild Allh from the gProjecth menu at the top of the screen.

    Figure 39e

    Figure 39

    14. Turn on the Atlys, and insert to the connector to PROG port. Select the gProgram FPGAh from gXilinx
          Toolsh in the menu at the top of the screen.

    Figure 40e

    Figure 40

    15. Select the file to be written.

    Text 2

          After Selection, click the gProgramh. Then the file is written to FPGA.

    Figure 41e

    Figure 41

    16. Expand gempty_application_0h in gProject Explorerh, and right-click the item gempty_application_0.elfh
          from gBinaries g. Select gRun Ash?hLaunch on Hardwareh, and source code is written to the FPGA.

    Figure 42e

    Figure 42


  • Creating a new ISE project

    • Because HW part and MicroBlaze are cannot connected for demo project, the ISE@is needed to setup.


    1. Launch ISE. gNew Project Wizardh is launched when select the gFileg?hNew Projecth from the menu at
          the top of the screen.

    2. In page of the gCreate New Projecth, set the project name and location of the save folder.
          After you verify the Top-level source type is set to HDL ,and click gNexth.

    Figure 43e

    Figure 43

    3. In page of the gProject Settingsh, set up the target device and development tools. Set as shown, and
          then click gNexth.

    Figure 44e

    Figure 44

    4. In page of the Project Summary, Click the gFinishh after checking the setting error. After that, close
          gNew Project Wizardh.

    Figure 45e

    Figure 45

    At this point, empty project of ISE is created.

    Figure 46

    Figure 46


  • Integration of EDK and ISE project

    • In the foregoing paragraph, you generated an empty ISE project. Next, you should add an EDK project (system.xmp) to the ISE project (noise_cancelling.xise). The procedures are as follows.


    1. You should copy Atlys_AC97_EDK_demo\project folder into the folder of ISE project. We changed the
          name of this folder to Demo this time.

    2. You should start ISE project, and click Project ¨ Add Source from a menu of the upper part of the
          screen. You should choose system.xmp in the Demo folder which you copied just now.

    Figure 47e

    Figure 47

    3. You will be able to confirm that EDK is added to ISE project.

    Figure 48e

    Figure 48

    As a result, you can connect the HW part that is designed on ISE and the circuit of the EDK project.

    Figure 49e

    Figure 49


  • Setting of the peripheral on XPS taken in ISE

    • You add interface for the outside of the EDK project circuit in XPS to connect the HW part to a CPU. We will explain about how to connect on ISE in the next clause (Integration of HW circuit at the ISE).

    Figure 50e

    Figure 50


    1.You should click the system in Hierarchy of the ISE, and XPS will starts when you choose Manage
          Processor Design (xps) from Processes.

    Figure 51e

    Figure 51

    2. You should make the peripheral in reference to
          "Create and Import Peripheral For Microblaze ver AXI.ppt(here)".

    3. You should right-click on the IP which you want to add from IP Catalog column, and click on Add IP to
          add a peripheral.

    Figure 52e

    Figure 52

    4. The setting window should be displayed, depending on your choice of IP, so you set it.

    Figure 53e

    Figure 53

    5. The peripheral should be added. When you want to change setting, you should right-click and click
          on Configure IP. It is deleted by Delete Instance.

    Figure 54e

    Figure 54

    6. You can set the the connection setting of the peripheral in the Ports tab. The port of the peripheral is
          displayed when you open the peripheral which you want to set the connection setting. When there is the
          port which you want to connect in XPS, you should set connection from New Connection or choices.
          If you want to connect in outside of XPS project, you should choose Make External.

    Figure 55e

    Figure 55

    7. If you chose Make External, it is added to the item of External Ports.

    Figure 56e

    Figure 56

    8. In this case, we use the test IP which we made in cause 2. First, you should add six test IPs, and change
          the name as follows.

    Figure 57e

    Figure 57

    Text 3

    9. You should set the port in reference to cause 6`7.
          win_out, ifft_re_out, ifft_im_out sets the following ports as External Ports.

    Text 4

          HO_in, fft_re_in, fft_im_in sets the following ports as External Ports.

    Text 4

    10. If you finished to design in XPS, you should choose Hardware ¨ Generate Netlist in the menu of the
          upper part of the screen and generate the netlist.

    Figure 58e

    Figure 58

    11. You should close the XPS.

    12. You should click system in Hierarchy of ISE and choose Generate Top HDL Source from Processes.

    Figure 59e

    Figure 59

    13. system_top.v should be generated. This file is generated in Demo folder. You should copy this in the
          folder of the ISE project.

    Figure 60e

    Figure 60

    14. You should right-click on system_top.v of the Hierarchy, and exclude it from a project by gRemoveh.
          After that, you should add the system_top.v file under the ISE project folder in Add Source. This
          system_top module becomes the top module of the system which you develop.


  • Integrate of HW circuit and the circuit in XPS which you made in the foregoing paragraph by ISE

    • We connect HW circuit which you made in section 3-1-1. and the circuit in XPS which you made in the foregoing paragraph on ISE.

    Figure 61e

    Figure 61

    1. We copy edf file which you made in symphony to ISE project folder, and we add it to the project by Add
          Source.

    2. Describe the module of this circuit(Model-Base-RTL design) into system_top.v by verilog, and connect it
          and the port of the circuit which you made in XPS project.
          We can download the circuit time of the top module(here) which we make in this time from here.

    Figure 62e

    Figure 62

    3. We can check the circuit structure in View RTL Schematic in Synthesize-XST or Processes tab.

    Figure 63e

    Figure 63


  • Configuration

    • 1. We select system_top in Hierarchy, and right-click Generate Programing File in Processes tab, and run
          Rerun All.

    Figure 64e

    Figure 64

    2. If there is no error, system_top.bit is created in ISE project folder.


    Completed implementation of HW.