10. DESIGN SPECIFICATIONS

10.1 SPEED AND AREA UNIT

Since it is impossible to use the same synthesis library for various participants,

• Use 1 exor gate delay as a 1 UNIT_DELAY for speed comparison
• Use 1 exor gate area as a 1 UNIT_AREA for area comparison
• How to measure 1 exor gate delay
1. Synthesize the 50 inputs exor gates
2. Measure the total delay time
3. UNIT_DELAY is obtained by total delay divided by the number of stages
4. UNIT_AREA is obtained by the total area divide by number of exor gates
• VHDL code for 50 inputs exor :parity.vhd
• Example of synthesized circuit :PDF,PS
• Example of critical path delay measurement :report timing
• Example of circuit area measurement :report area

In the previous example, total delay = 7.17 ns and 6 circuit stages, then the 7.17/6= 1.195 ns is the UNIT_DELAY of the speed. Please normalize your circuit speed by this UNIT_DELAY.

In the example, total cell area = 147.0 and 49 EXOR gates. Then 147.0/49=3.0 is the UNIT_AREA. Please normalize your circuit area by this UNIT_AREA.

10.2 NOTES WHEN YOU USE RAM/ROM

In order to make easy comparison among many design entries, please use the following guide :

• Do not use H/W macro RAM. Use synthesizable RAM description and synthesize your RAM using Flip-flops.
• If you cannot use synthesizable RAM for your design, please state the reason clearly in your report.
• Do not use H/W macro ROM. Realize the ROM by synthesized combinational logic.